View AT25640A_387982.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Features
* Serial Peripheral Interface (SPI) Compatible * Supports SPI Modes 0 (0,0) and 3 (1,1)
- Data Sheet Describes Mode 0 Operation
* Medium-voltage and Standard-voltage Operation * * * * * * * *
- 2.7 (VCC = 2.7V to 5.5V) Extended Temperature Range -40C to 125C 5.0 MHz Clock Rate 32-byte Page Mode Block Write Protection - Protect 1/4, 1/2, or Entire Array Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software Data Protection Self-timed Write Cycle (2 ms [5V] typical) High Reliability - Endurance: One Million Write Cycles - Data Retention: 100 Years 8-lead PDIP, 8-lead JEDEC SOIC Packages and 8-lead TSSOP Packages
Description
The AT25080A/160A/320A/640A provides 8192/16384/32768/65536 bits of serial electrically-erasable programmable read-only memory (EEPROM) organized as 1024/2048/4096/8192 words of 8 bits each. The device is optimized for use in many automotive applications where low-power and low-voltage operation are essential. The AT25080A/160A/320A/640A is available in space-saving 8-lead PDIP, 8-lead JEDEC SOIC and 8-lead TSSOP packages. The AT25080A/160A/320A/640A is enabled through the Chip Select pin (CS) and accessed via a three-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All programming cycles are completely selftimed, and no separate erase cycle is required before write. Block write protection is enabled by programming the status register with one of four blocks of write protection. Separate program enable and program disable instructions are provided for additional data protection. Hardware data protection is provided via the WP pin to protect against inadvertent write attempts to the status register. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence. Table 1. Pin Configurations
Pin Name CS SCK SI SO GND VCC WP HOLD NC DC Function Chip Select Serial Data Clock Serial Data Input Serial Data Output Ground Power Supply Write Protect Suspends Serial Input No Connect Don't Connect
CS SO WP GND CS SO WP GND
SPI Serial Extended Temperature EEPROMs 8K (1024 x 8) 16K (2048 x 8) 32K (4096 x 8) 64K (8192 x 8) AT25080A AT25160A AT25320A AT25640A
8-lead PDIP
1 2 3 4 8 7 6 5 VCC HOLD SCK SI
8-lead SOIC
CS SO WP GND 1 2 3 4 8 7 6 5 VCC HOLD SCK SI
8-lead TSSOP
1 2 3 4 8 7 6 5 VCC HOLD SCK SI
5082B-SEEPR-1/05
1
Absolute Maximum Ratings*
Operating Temperature......................................-40C to +125C Storage Temperature .........................................-65C to +150C Voltage on Any Pin with Respect to Ground ........................................ -1.0V to +7.0V Maximum Operating Voltage .......................................... 6.25V DC Output Current........................................................ 5.0 mA *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Figure 1. Block Diagram
2
AT25080A/160A/320A/640A
5082B-SEEPR-1/05
AT25080A/160A/320A/640A
Table 2. Pin Capacitance(1) Applicable over recommended operating range from TAE = 25C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted)
Symbol COUT CIN Note: Test Conditions Output Capacitance (SO) Input Capacitance (CS, SCK, SI, WP, HOLD) 1. This parameter is characterized and is not 100% tested. Max 8 6 Units pF pF Conditions VOUT = 0V VIN = 0V
Table 3. DC Characteristics Applicable over recommended operating range from: TAE = -40C to +125C, VCC = +2.7V to +5.5V
Symbol VCC1 ICC1 ICC2 ICC3 ISB1 ISB2 IIL IOL VIL
(2)
Parameter Supply Voltage Supply Current Supply Current Supply Current Standby Current Standby Current Input Leakage Output Leakage Input Low-voltage Input High-voltage Output Low-voltage Output High-voltage
Test Condition
Min 2.7
Typ
Max 5.5 6.0 3.0 7.0
Units V mA mA mA A A A
VCC = 5.0V at 5 MHz, SO = Open, Read VCC = 5.0V at 1 MHz VCC = 5.0V at 5 MHz, SO = Open, Read, Write VCC = 2.7V, CS = VCC VCC = 5.0V, CS = VCC VIN = 0V to VCC VIN = 0V to VCC -3.0 -3.0 -0.6 VCC x 0.7 2.7V VCC 5.5V IOL = 3.0 mA IOH = -1.6 mA VCC - 0.8 0.2 2.0
10.0(1) 13.0(1)
3.0 VCC x 0.3 VCC + 0.5 0.4
A V V V V
VIH(2) VOL1 VOH1 Note:
1. Worst case measured at 125C 2. VIL min and VIH max are reference only and are not tested.
3
5082B-SEEPR-1/05
Table 4. AC Characteristics Applicable over recommended operating range from TAE = -40C to +125C, VCC = As Specified, CL = 1 TTL Gate and 100 pF (unless otherwise noted).
Symbol Parameter SCK Clock Frequency Input Rise Time Input Fall Time SCK High Time SCK Low Time CS High Time CS Setup Time CS Hold Time Data In Setup Time Data In Hold Time Hold Setup Time Hold Hold Time Output Valid Output Hold Time Hold to Output Low Z Hold to Output High Z Output Disable Time Write Cycle Time 5.0V, 25C, Page Mode Voltage 2.7-5.5 2.7-5.5 2.7-5.5 2.7-5.5 2.7-5.5 2.7-5.5 2.7-5.5 2.7-5.5 2.7-5.5 2.7-5.5 2.7-5.5 2.7-5.5 2.7-5.5 2.7-5.5 2.7-5.5 2.7-5.5 2.7-5.5 2.7-5.5 1M 40 40 80 80 80 5 20 40 40 0 0 0 40 80 80 5 40 Min 0 Max 5.0 2 2 Units MHz s s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms Write Cycles
fSCK tRI tFI tWH tWL tCS tCSS tCSH tSU tH tHD tCD tV tHO tLZ
tHZ tDIS tWC Endurance(1) Note:
1. This parameter is characterized and is not 100% tested.
4
AT25080A/160A/320A/640A
5082B-SEEPR-1/05
AT25080A/160A/320A/640A
Serial Interface Description
MASTER: The device that generates the serial clock. S L AV E : B e c a u s e t h e s e r i a l c l o c k p i n ( S C K ) i s a l w a y s a n i n p u t , t h e AT25080A/160A/320A/640A always operates as a slave. TRANSMITTER/RECEIVER: The AT25080A/160A/320A/640A has separate pins designated for data transmission (SO) and reception (SI). MSB: The Most Significant Bit (MSB) is the first bit transmitted and received. SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be received. This byte contains the op-code that defines the operations to be performed. INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the AT25080A/160A/320A/640A, and the serial output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again. This will reinitialize the serial communication. CHIP SELECT: The AT25080A/160A/320A/640A is selected when the CS pin is low. When the device is not selected, data will not be accepted via the SI pin, and the serial output pin (SO) will remain in a high impedance state. HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25080A/160A/320A/640A. When the device is selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state. WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations when held high. When the WP pin is brought low and WPEN bit is "1", all write operations to the status register are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is blocked when the WPEN bit in the status register is "0". This will allow the user to install the AT25080A/160A/320A/640A in a system with the WP pin tied to ground and still be able to write to the status register. All WP pin functions are enabled when the WPEN bit is set to "1".
5
5082B-SEEPR-1/05
Figure 2. SPI Serial Interface
AT25080A/160A/320A/640A
6
AT25080A/160A/320A/640A
5082B-SEEPR-1/05
AT25080A/160A/320A/640A
Functional Description
The AT25080A/160A/320A/640A is designed to interface directly with the synchronous serial peripheral interface (SPI) of the 6805 and 68HC11 series of microcontrollers. The AT25080A/160A/320A/640A utilizes an 8-bit instruction register. The list of instructions and their operation codes are contained in Table 5. All instructions, addresses, and data are transferred with the MSB first and start with a high-to-low CS transition. Table 5. Instruction Set for the AT25080A/160A/320A/640A
Instruction Name WREN WRDI RDSR WRSR READ WRITE Instruction Format 0000 X110 0000 X100 0000 X101 0000 X001 0000 X011 0000 X010 Operation Set Write Enable Latch Reset Write Enable Latch Read Status Register Write Status Register Read Data from Memory Array Write Data to Memory Array
WRITE ENABLE (WREN): The device will power up in the write disable state when VCC is applied. All programming instructions must therefore be preceded by a Write Enable instruction. WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable instruction disables all programming modes. The WRDI instruction is independent of the status of the WP pin. READ STATUS REGISTER (RDSR): The Read Status Register instruction provides access to the status register. The READY/BUSY and Write Enable status of the device can be determined by the RDSR instruction. Similarly, the block write protection bits indicate the extent of protection employed. These bits are set by using the WRSR instruction. Table 6. Status Register Format
Bit 7 WPEN Bit 6 X Bit 5 X Bit 4 X Bit 3 BP1 Bit 2 BP0 Bit 1 WEN Bit 0 RDY
Table 7. Read Status Register Bit Definition
Bit Bit 0 (RDY) Bit 1 (WEN) Bit 2 (BP0) Bit 3 (BP1) Definition Bit 0 = "0" (RDY) indicates the device is ready. Bit 0 = "1" indicates the write cycle is in progress. Bit 1= "0" indicates the device is not write-enabled. Bit 1 = "1" indicates the device is write-enabled. See Table 8 on page 8. See Table 8 on page 8.
Bits 4 - 6 are "0"s when device is not in an internal write cycle. Bit 7 (WPEN) See Table 9 on page 8. Bits 0 - 7 are "1"s during an internal write cycle.
7
5082B-SEEPR-1/05
WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of four levels of protection. The AT25080A/160A/320A/640A is divided into four array segments. One-quarter, one-half, or all of the memory segments can be protected. Any of the data within any selected segment will therefore be read only. The block write protection levels and corresponding status register control bits are shown in Table 8. Bits BP0, BP1, and WPEN are nonvolatile cells that have the same properties and functions as the regular memory cells (e.g., WREN, tWC, RDSR). Table 8. Block Write Protect Bits
Status Register Bits Level 0 1 (1/4) 2 (1/2) 3 (All) BP1 0 0 1 1 BP0 0 1 0 1 AT25080A None 0300 - 03FF 0200 - 03FF 0000 - 03FF Array Addresses Protected AT25160A None 0600 - 07FF 0400 - 07FF 0000 - 07FF AT25320A None 0C00 - 0FFF 0800 - 0FFF 0000 - 0FFF AT25640A None 1800 - 1FFF 1000 - 1FFF 0000 - 1FFF
The WRSR instruction also allows the user to enable or disable the write protect (WP) pin through the use of the write protect enable (WPEN) bit. Hardware write protection is enabled when the WP pin is low and the WPEN bit is "1". Hardware write protection is disabled when either the WP pin is high or the WPEN bit is "0". When the device is hardware write protected, writes to the status register, including the block protect bits and the WPEN bit, and the block-protected sections in the memory array are disabled. Writes are only allowed to sections of the memory that are not block-protected. NOTE: When the WPEN bit is hardware write protected, it cannot be changed back to "0" as long as the WP pin is held low. Table 9. WPEN Operation
WPEN 0 0 1 1 X X WP X X Low Low High High WEN 0 1 0 1 0 1 Protected Blocks Protected Protected Protected Protected Protected Protected Unprotected Blocks Protected Writeable Protected Writeable Protected Writeable Status Register Protected Writeable Protected Protected Protected Writeable
8
AT25080A/160A/320A/640A
5082B-SEEPR-1/05
AT25080A/160A/320A/640A
READ SEQUENCE (READ): Reading the AT25080A/160A/320A/640A via the serial output (SO) pin requires the following sequence. After the CS line is pulled low to select a device, the read op-code is transmitted via the SI line followed by the byte address to be read (A15-A0, see Table 10). Upon completion, any data on the SI line will be ignored. The data (D7-D0) at the specified address is then shifted out onto the SO line. If only one byte is to be read, the CS line should be driven high after the data comes out. The read sequence can be continued since the byte address is automatically incremented and data will continue to be shifted out. When the highest address is reached, the address counter will roll over to the lowest address, allowing the entire memory to be read in one continuous read cycle. WRITE SEQUENCE (WRITE): In order to program the AT25080A/160A/320A/640A, two separate instructions must be executed. First, the device must be write enabled via the WREN instruction. Then a Write (WRITE) instruction may be executed. Also, the address of the memory location(s) to be programmed must be outside the protected address field location selected by the block write protection level. During an internal write cycle, all commands will be ignored except the RDSR instruction. A Write instruction requires the following sequence. After the CS line is pulled low to select the device, the WRITE op-code is transmitted via the SI line followed by the byte address (A15-A0) and the data (D7-D0) to be programmed (See Table 10). Programming will start after the CS pin is brought high. The low-to-high transition of the CS pin must occur during the SCK low-time immediately after clocking in the D0 (LSB) data bit. The READY/BUSY status of the device can be determined by initiating a read status register (RDSR) instruction. If Bit 0 = "1", the write cycle is still in progress. If Bit 0 = "0", the write cycle has ended. Only the RDSR instruction is enabled during the write programming cycle. The AT25080A/160A/320A/640A is capable of a 32-byte page write operation. After each byte of data is received, the five low-order address bits are internally incremented by one; the high-order bits of the address will remain constant. If more than 32 bytes of data are transmitted, the address counter will roll over and the previously written data will be overwritten. The AT25080A/160A/320A/640A is automatically returned to the write disable state at the completion of a write cycle. NOTE: If the device is not write enabled (WREN), the device will ignore the write instruction and will return to the standby state, when CS is brought high. A new CS falling edge is required to reinitiate the serial communication. Table 10. Address Key
Address AN Don't Care Bits AT25080A A9-A0 A15-A10 AT25160A A10-A0 A15-A11 AT25320A A11-A0 A15-A12 AT25640A A12-A0 A15-A13
9
5082B-SEEPR-1/05
Timing Diagrams
Figure 3. Synchronous Data Timing (for Mode 0)
VIH CS VIL t CSS VIH SCK VIL t SU VIH SI VIL tV VOH SO VOL HI-Z t HO t DIS HI-Z VALID IN tH t WH t WL t CSH t CS
Figure 4. WREN Timing
Figure 5. WRDI Timing
10
AT25080A/160A/320A/640A
5082B-SEEPR-1/05
AT25080A/160A/320A/640A
Figure 6. RDSR Timing
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
SI
INSTRUCTION
DATA OUT
SO
HIGH IMPEDANCE
7
MSB
6
5
4
3
2
1
0
Figure 7. WRSR Timing
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
DATA IN
SI
INSTRUCTION
7
6
5
4
3
2
1
0
HIGH IMPEDANCE
SO
11
5082B-SEEPR-1/05
Figure 8. READ Timing
CS
0 SCK
1
2
3
4
5
6
7
8
9 10 11 20 21 22 23 24 25 26 27 28 29 30 31
BYTE ADDRESS
SI
INSTRUCTION
15 14 13 ...
3
2
1
0
DATA OUT HIGH IMPEDANCE
SO
7
6
5
4
3
2
1
0
MSB
Figure 9. WRITE Timing
CS
0
1
2
3
4
5
6
7
8
9 10 11 20 21 22 23 24 25 26 27 28 29 30 31
SCK
BYTE ADDRESS
DATA IN
SI
INSTRUCTION
15 14 13 ...
3
2
1
0
7
6
5
4
3
2
1
0
SO
HOLD Timing
HIGH IMPEDANCE
CS
SCK
HOLD
SO
12
AT25080A/160A/320A/640A
5082B-SEEPR-1/05
AT25080A/160A/320A/640A
AT25080A Ordering Information
Ordering Code AT25080A-10PE-2.7 AT25080AN-10SE-2.7 AT25080A-10PQ-2.7(1) AT25080AN-10SQ-2.7(1) AT25080A-10TQ-2.7(1) Notes: 1. "Q" designates Green package + RoHS compliant. Package 8P3 8S1 8P3 8S1 8A2 Operation Range Extended Temperature (-40C to 125C) Lead-free/Halogen-free Extended Temperature (-40C to 125C)
Package Type 8P3 8S1 8A2 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) Options -2.7 Low Voltage (2.7V to 5.5V)
13
5082B-SEEPR-1/05
AT25160A Ordering Information
Ordering Code AT25160A-10PE-2.7 AT25160AN-10SE-2.7 AT25160A-10PQ-2.7(1) AT25160AN-10SQ-2.7(1) AT25160A-10TQ-2.7(1) Notes: 1. "Q" designates Green package + RoHS compliant. Package 8P3 8S1 8P3 8S1 8A2 Operation Range Extended Temperature (-40C to 125C) Lead-free/Halogen-free Extended Temperature (-40C to 125C)
Package Type 8P3 8S1 8A2 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) Options -2.7 Low Voltage (2.7V to 5.5V)
14
AT25080A/160A/320A/640A
5082B-SEEPR-1/05
AT25080A/160A/320A/640A
AT25320A Ordering Information
Ordering Code AT25320A-10PE-2.7 AT25320AN-10SE-2.7 AT25320A-10PQ-2.7(1) AT25320AN-10SQ-2.7(1) AT25320A-10TQ-2.7(1) Notes: 1. "Q" designates Green package + RoHS compliant. Package 8P3 8S1 8P3 8S1 8A2 Operation Range Extended Temperature (-40C to 125C) Lead-free/Halogen-free Extended Temperature (-40C to 125C)
Package Type 8P3 8S1 8A2 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) Options -2.7 Low Voltage (2.7V to 5.5V)
15
5082B-SEEPR-1/05
AT25640A Ordering Information
Ordering Code AT25640A-10PE-2.7 AT25640AN-10SE-2.7 AT25640A-10PQ-2.7(1) AT25640AN-10SQ-2.7(1) AT25640A-10TQ-2.7(1) Note: 1. "Q" designates Green package + RoHS compliant. Package 8P3 8S1 8P3 8S1 8A2 Operation Range Extended Temperature (-40C to 125C) Lead-free/Halogen-free Extended Temperature (-40C to 125C)
Package Type 8P3 8S1 8A2 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) Options -2.7 Low Voltage (2.7V to 5.5V)
16
AT25080A/160A/320A/640A
5082B-SEEPR-1/05
AT25080A/160A/320A/640A
Packaging Information
8P3 - PDIP
E E1
1
N
Top View
c eA
End View
D e D1 A2 A
SYMBOL
COMMON DIMENSIONS (Unit of Measure = inches) MIN - NOM - MAX NOTE
A A2 b b2 b3 c D
0.210 0.195 0.022 0.070 0.045 0.014 0.400
-
2
0.115 0.014 0.045 0.030 0.008 0.355 0.005 0.300 0.240
0.130 0.018 0.060 0.039 0.010 0.365
-
5 6 6
3 3 4 3
b2 b3
4 PLCS
L
D1 E E1 e eA L
b
0.310 0.250 0.100 BSC 0.300 BSC
0.325 0.280
Side View
4 0.150 2
0.115
0.130
Notes:
1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information. 2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02 2325 Orchard Parkway San Jose, CA 95131 TITLE 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) DRAWING NO. 8P3 REV. B
R
17
5082B-SEEPR-1/05
8S1 - JEDEC SOIC
C
1
E
E1
N
L
Top View End View
e B A
SYMBOL COMMON DIMENSIONS (Unit of Measure = mm) MIN 1.35 0.10 0.31 0.17 4.80 3.81 5.79 NOM - - - - - - - 1.27 BSC 0.40 0 - - 1.27 8 MAX 1.75 0.25 0.51 0.25 5.00 3.99 6.20 NOTE
A1
A A1 b C
D
D E1 E
Side View
e L
Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
10/7/03 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) DRAWING NO. 8S1 REV. B
R
18
AT25080A/160A/320A/640A
5082B-SEEPR-1/05
AT25080A/160A/320A/640A
8A2 - TSSOP
3 21
Pin 1 indicator this corner
E1
E
L1
N L
Top View
End View
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN 2.90 NOM 3.00 6.40 BSC 4.30 - 0.80 0.19 4.40 - 1.00 - 0.65 BSC 0.45 0.60 1.00 REF 0.75 4.50 1.20 1.05 0.30 4 3, 5 MAX 3.10 NOTE 2, 5
b
A
D E E1 A
e D
A2
A2 b e
Side View
L L1
Notes:
1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm. 5. Dimension D and E1 to be determined at Datum Plane H. 5/30/02
R
2325 Orchard Parkway San Jose, CA 95131
TITLE 8A2, 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)
DRAWING NO. 8A2
REV. B
19
5082B-SEEPR-1/05
Atmel Corporation
2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600
Atmel Operations
Memory
2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314
RF/Automotive
Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759
Regional Headquarters
Europe
Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500
Microcontrollers
2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60
Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom
Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France Tel: (33) 4-76-58-30-00 Fax: (33) 4-76-58-34-80
Asia
Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369
ASIC/ASSP/Smart Cards
Zone Industrielle 13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00 Fax: (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743
Japan
9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581
Literature Requests
www.atmel.com/literature
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL'S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL'S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Atmel's products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.
(c) Atmel Corporation 2005. All rights reserved. Atmel (R), logo and combinations thereof are registered trademarks, and Everywhere You Are SM is a trademark of Atmel Corporation or its subsidiaries. Other terms and product names may be the trademarks of others.
Printed on recycled paper.
5082B-SEEPR-1/05

▲Up To Search▲

Price & Availability of AT25640A

	To Download AT25640A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .